The DASC sponsors Working Groups that undertake the technical work of standards development. Each Working Group is assigned one or more standards projects. A project is designated by its IEEE-assigned number prefixed with the letter "P".

The current Working Groups are listed below, with links to their web sites:

• VHDL Working Groups
  • P1076 Standard VHDL Language Reference Manual (VASG)
  • P1076.1 Standard VHDL Analog and Mixed-Signal Extensions (VHDL-AMS)
  • P1076.1.1 Standard VHDL Analog and Mixed-Signal Extensions - Packages for Multiple Energy Domain Support (StdPkgs) - this group is now part of 1076.1
  • P1076.4 Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification (VITAL) - This group is now part of 1076.
  • VHDL-200x: the next revision
  • Issues Screening and Analysis Committee (ISAC)
  • VHDL Programming Language Interface Task Force (VHPI)
• SystemVerilog Working Groups
  • P1800 SystemVerilog: Unified Hardware Design, Specification and Verification Language (SV-IEEE1800) [cosponsored with IEEE-SA CAG]
  • P1364 Standard for Verilog Hardware Description Language (IEEEVerilog)
• P1481 Standard for Integrated Circuit (IC) Open Library Architecture (OLA) (IEEE1481R)

• P1647 Standard for the Functional Verification Language 'e' (eWG)

• P1666 Standard System C Language Reference Manual (systemc)

• P1685 SPIRIT XML Standard for IP Description (IEEE-1685)

• P1699 Rosetta System Level Design Language Standard

• P1735 Recommended Practice for Encryption and [Use Rights] Management of Electronic Design Intellectual Property (IP)

• P1778 ESTEREL v7 Language Standardization

• P1801 Standard for the Design & Verification of Low Power ICs
• P1850 Standard for PSL: Property Specification Language (IEEE-1850)

Links to web pages of inactive Working Groups:

• P1076.2 IEEE Standard VHDL Mathematical Packages (math)

• P1076.3 Standard VHDL Synthesis Packages (vhdlsynth)

• P1164 Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) (vhdl-std-logic)

• P1364.1 Standard for Verilog Register Transfer Level Synthesis (VLOG-Synth)

• P1497 Standard for Standard Delay Format (SDF) for the Electronic Design Process (sdf)

• P1499 Standard Interface for Hardware Description Models of Electronic Components (OMF)

• P1577 Object Oriented VHDL (oovhdl)

• P1603 Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks (ALF)

• P1604 Library IEEE (libieee)

• P1076.6 Standard for VHDL Register Transfer Level (RTL) Synthesis (SIWG)