From: owner-stds-dasc-sc@server.eda.org on behalf of John Willis
[john.willis@ftlsys.com]
Sent: Thursday, 19 February 2004 7:42
To: stds-dasc-sc@server.eda.org
Subject: Re: DASC-SC Meeting / VHDL-RF/MW PAR

Peter,

In order to best explain the VHDL-RF/MW PAR and provide
more time for people to read through the PAR, I propose
to present it at the next meeting.

Although I could not schedule the travel, I will plan
to dial-in from 18:00 to 21:00 BST today.

VHDL-RF/MW Report:

The VHDL-RF/MW group is ready to submit a PAR cover
extensions to VHDL and VHDL-AMS which provide language
representation capability required for electronic
designs where non-lumped behavior and frequency-domain
modeling are appropriate.  The standard style will use
prose specification to avoid standardization of a specific
implementation.


Best regards, John

-----------------------------------------------------------
John Willis                     jwillis@ftlsys.com
FTL Systems Inc.                FTL Systems UK Ltd
1620 Greenview Drive SW         2 Venture Road
Rochester, MN 55902             Chilworth Science Park
United States                   United Kingdom
1.507.288.3154 (Voice)          44.2380.767.700(Voice)
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http://www.ftlsystems.com       http://www.ftlsystems.co.uk