Contents |
Esterel v7 provides industrial users with a new integrated and formal way to specify, design, simulate, formally verify, and synthesize complex hardware IPs, systems of IPs, embedded software, and systems with a changing mix of hardware and software. Typical applications are memory control, DMAs, bus and network interfaces, peripheral access protocols, cache and pipeline control, hardware- or software-based power management, software / hardware transactors, device drivers, embedded controllers, etc. Esterel v7 is particularly adapted to the specification and verification of any hardware or software system exhibiting complex temporal behavior, with large-scale concurrency, communication, and synchronization. Since the Esterel flow is fully compatible with current hardware and software flows, CAD tool vendors can seamlessy add Esterel-based high-level specification tools to their current set of tools. An additional benefit for academia is to provide a better integration of fundamental concepts that are usually teached differently in different courses: embedded systems software, electronic systems design, and formal verification for instance. Widesprerad interest for Esterel v7 is demonstrated by the current interest of industrial and academic users to participate in the IEEE standardization workgroup, by the Esterel industrial designs already realized within the Esterel Consortium, by the comprehensive literature related to Esterel, and by the strong Esterel presence in teaching institutions.
[edit]Esterel v7 can and should be compiled to other standard languages, such as Verilog (P1364), System Verilog(P1800), VHDL (P1076b), C, C++, SystemC (P1666), or Java. When compiled to any of these target languages, an Esterel programs behaves as any hand-written program, usable through a simple Application Programming Interface (API). Therefore, the use of Esterel v7 does not prevent in ay way the use of any other standard.
[edit]The Esterel language is completely distinct from all existing HDLs and software programming languages, in particular in its way to marry sequencing, synchronous concurrency, communication, and exception handling.
[edit]There is a large amount of publications on Esterel. The technical feasibility of Esterel v7 language design, implementation, and usability has already been proven by its usage for industrial designs based on the Esterel Studio tool of Esterel Technologies. Evolutions of the language towards the standard are expected to remain local, and their feasibility in terms of design soudness, hardware synthesizability, and software implementability are not expected to give difficult technical problems.
Several academic compilers are available for the previous version Esterel v5 of Esterel, some of them in open source. This should help anyone who wants to implement a compiler. Furthermore, a book called Compiling Esterel is about to appear, co-signed by D. Potop (INRIA), S. Edwards (Columbia U.), and G. Berry (Esterel Technologies), all independent Esterel compiler writers.
[edit]There are currently 18 workgroup volunteers with extensive personal experience of Esterel, 10 industrials and 8 academics. The industrial members belong to Esterel Technologies, General Motors, IBM, Intel, Microsoft, NEC, NXP, Orange, ST Microeclectronics, Texas Instruments. The Academics belong to Christian Albrechts University (Germany), Columbia University (USA), Ecole d'Ingénieurs de Genève (Switzerland), INRIA (France), Kaiserlautern University (Germany), Technion (Israël), Tübingen University (Germany), and Université de Nice (France),
[edit]The expected timeframe is 2 years. It seems reasonable since the Esterel v7 language has been stable for two years by now. Minor modification have already been requested and their initial study is on the way. They should remain local and raise no conceptual problem. The current Esterel v7 LRM is available and has been read and commented by many users. Putting it in IEEE format and amending it according to the workgroup resolutions should not fundamentally change its technical structure. It looks clearly feasible in 2 years
Retrieved from "http://monster/mwiki/index.php/Esterel_v7_Standardization_Report"